Webb9 maj 2011 · I'm just trying to get an FFT up and running, and I basically copied and pasted the code for the cfft function from the DSP library reference (code is shown far below). … WebbIf that is useful I dunno. Like with the double buffers around the ffts is an extra 4k on the stack . I'm not using the TCM on the device either yes, and then the data access would be have to go through the cache. perhaps another 10%.... out of interest, my old sweetheart the ADI SHARC would do the 512 pt complex fft in perhaps 8000 cycles ?

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http://ee.mweda.com/rd/146627_2.html WebbIn round terms, this is about a factor of five greater than for a single FFT of 512 points. Since the real FFT requires about 12 clock cycles per sample, FFT convolution can be carried out in about 60 clock cycles per sample. For a 2106x SHARC DSP at 40 MHz, this corresponds to a data throughput of approximately 660k samples/second. on this campus

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Webb目前 ADI 主流的 DSP 是 Sharc 系列，其中的 ADSP-2146x 系列性能达到 2700MFLOPS， 与 TI 的 C674x 在 1k 点 复数FFT 的耗时都是 24us，针锋相对，旗鼓相当。 而 SC58x 的双核 DSP 里的 FFT 硬核加速器，只需要 5.5us 就可以完成了，比 TI 1GHz 的高性能 C66x 的速度 … WebbHigh performance 32-bit/40-bit floating-point processor optimized for high performance audio processing Single-instruction, multiple-data (SIMD) computational architecture 5 … Webbhttp://www.analog.com/en/products/processors-dsp/sharc/ADSP-SC5html It has an ARM with DSP Periperals as will as two DSP cores. The accelerators are separate entities from the DSP cores. These devices have FFT, FIR and DSP accelerators. The ARM can off-load these mundane DSP tasks to the accelerators. on this calendar